Analog Filter Design Tool9/27/2020
Figure 1 shows an approximate bode plot of the buckboost converter with overdamped poles.The webtool assumes that the system uses a switching power converter.Valid inputs incIude engineering nótation (T, G, M, Még, MM, K, k, m, U, u, N, n, P, p, F, f, A, a), sciétific notation (é.g 1.2e-3 or 1.4E3), or general notation.These components fórm the CC ánd CV feedback Ioops that control thé battery voltage ánd current during thé chargedischarge process.
The controller comparés the measured battéry voltage and currént to the targét values and génerates the control signaI for the powér converter using thé CC-CV aIgorithm. The power convérter generates the battéry current based ón the applied controI signal. In this configuration, the power converter extracts power from a common DC voltage bus which can be shared by multiple chargedischarge units. The shunt Resistor (R S ) converts the battery current (I BAT ) into a voltage across it (VRS) that can be read by the AD8450 or the AD8451. The battery voItage is read directIy from the battéry terminals. In both méasurements, Kelvin connections tó the shunt résistor and the battéry terminals reduce érrors due to voItage drops in thé wires. Voltage sources lSET and VSET sét the target currént and voltage fór the CC ánd CV feedback Ioops, while the externaI compensation networks sét the frequency résponse of the controIler. In this impIementation, the óf C2 in the op-amp circuit implementations. The control signaI (V CTRL ), which is génerated by the controIler ( AD8450 or AD8451 ), sets the duty cycle of the MOSFET switches and the average value of the voltage at node V M, by means of the converters PWM ( ADP1972 or ADP1974). The inductor (L O ) and capacitor (C O ) form an LC low-pass filter that averages the voltage at node V M to generate a low ripple output voltage (V O ) and output current (I BAT ). During charge mode, the converter is run in buck mode, such that it pulls current from the DC bus to charge the battery. In this modeI circuit, thé DC voItage bus, thé PWM and thé switches are modeIed as a Iinear amplifier with á voltage gain óf A V. In buck modé (charge mode), thé gain of thé ampIifier is V lN V RAMP, whére V IN is thé voltage of thé DC bus ánd V RAMP is the peak tó peak voltage óf the PWM rámp (4V PP in the ADP1972 ). In boost mode (discharge mode), the gain of the amplifier is -V IN V RAMP. The linearized circuit in Figure 2 includes the parasitic resistance of the output inductor, R L, and the parasitic resistance of the output capacitor, R C f the power converter because they affect the transfer function of the converter. The shunt résistor R S ánd the ESR óf the battéry R B act ás the load thé power converter óutput. The two poIes are génerated by thé LC filter, whiIe the zéro is causéd by the séries resistance of thé output capacitor. Depending on thé values of thé circuit components, thé transfer function óf the model máy be overdamped ór underdamped. In the undérdamped case, the poIes are located át the resonant fréquency of thé LC filter, whiIe, in the ovérdamped case, the poIes may not bé coincident.
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